_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. max15070a/MAX15070B 7a sink, 3a source, 12ns, sot23 mosfet drivers general description the max15070a/MAX15070B are high-speed mosfet drivers capable of sinking 7a and sourcing 3a peak currents. the ics, which are an enhancement over max5048 devices, have inverting and noninverting inputs that provide greater flexibility in controlling the mosfet. they also feature two separate outputs work - ing in complementary mode, offering flexibility in control - ling both turn-on and turn-off switching speeds. the ics have internal logic circuitry that prevents shoot- through during output-state changes. the logic inputs are protected against voltage spikes up to +16v, regard - less of v+ voltage. propagation delay time is minimized and matched between the inverting and noninverting inputs. the ics have a very fast switching time, com - bined with short propagation delays (12ns typ), making them ideal for high-frequency circuits. the ics operate from a +4v to +14v single power supply and typically consume 0.5ma of supply current. the max15070a has standard ttl input logic levels, while the MAX15070B has cmos-like high-noise-margin (hnm) input logic levels. both ics are available in a 6-pin sot23 package and operate over the -40 n c to +125 n c temperature range. applications power mosfet switching switch-mode power supplies dc-dc converters motor control power-supply modules features s independent source and sink outputs s +4v to +14v single power-supply range s 7a peak sink current s 3a peak source current s inputs rated to +14v regardless of v+ voltage s 12ns propagation delay s matched delays between inverting and noninverting inputs within 500ps s hnm or ttl logic-level inputs s low-input capacitance: 10pf (typ) s thermal-shutdown protection s small sot23 package allows routing pcb traces underneath s -40 c to +125 c operating temperature range 19-5516; rev 1; 11/11 ordering information typical operating circuit note: all devices are specified over the -40c to +125c operating temperature range. + denotes a lead(pb)-free/rohs-compliant package. / v denotes an automotive-qualified part. evaluation kit available in+ n in- v+ v+ n_out gnd p_out max15070a MAX15070B part input logic levels pin-package max15070a aut+ ttl 6 sot23 max15070a aut/v+ 4-14v 6 sot23 MAX15070B aut+ hnm 6 sot23
max15070a/MAX15070B 7a sink, 3a source, 12ns, sot23 mosfet drivers 2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to gnd.) v+, in+, in- .......................................................... -0.3v to +16v n_out, p_out ........................................... -0.3v to (v+ + 0.3v) n_out continuous output current (note 1) ................. -200ma p_out continuous output current (note 1) ................ +125ma continuous power dissipation (t a = +70 n c) sot23 (derate 8.7mw/ n c above +70 n c) .................. 696mw* operating temperature range ...................... -40 n c to +125 n c junction temperature ................................................... +150 n c storage temperature range ........................... -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v+ = +12v, c l = 0f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c. parameters specified at v+ = +4.5v apply to the max15070a only; see figure 1.) (note 3) absolute maximum ratings note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . sot23 junction-to-ambient thermal resistance ( b ja ) ........ 115 n c/w junction-to-case thermal resistance ( b jc ) .................. 80 n c/w package thermal characteristics (note 2) * as per jedec 51 standard. note 1: continuous output current is limited by the power dissipation of the package. parameter symbol conditions min typ max units power supply (v+) input voltage range max15070a 4 14 v MAX15070B 6 14 undervoltage lockout v uvlo v+ rising 3.3 3.45 3.6 v undervoltage-lockout hysteresis 200 mv undervoltage lockout to output rising delay v+ rising 100 f s undervoltage lockout to output falling delay v+ falling 2 f s supply current i v+ v+ = 14v, no switching 0.5 1 ma v+ = 14v, switching at 1mhz 2.3 n-channel output (n_out) n_out resistance r n_out v+ = +12v, i n_out = -100ma t a = +25 n c 0.256 0.32 i t a = +125 n c 0.45 v+ = +4.5v, i n_out = -100ma t a = +25 n c 0.268 0.33 t a = +125 n c 0.465 power-off pulldown resistance v+ = unconnected, i n_out = -1ma, t a = +25 n c 1.3 1.9 k i output bias current i biasn v n_out = v+ 6 11 f a peak output current i peakn c l = 22nf 7.0 a
max15070a/MAX15070B 7a sink, 3a source, 12ns, sot23 mosfet drivers 3 electrical characteristics (continued) (v+ = +12v, c l = 0f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c. parameters specified at v+ = +4.5v apply to max15070a only, see figure 1.) (note 3) note 3: limits are 100% tested at t a = +25 c. limits over operating temperature range are guaranteed through correlation using the statistical quality control (sqc) method. note 4: design guaranteed by bench characterization. limits are not production tested. parameter symbol conditions min typ max units p-channel output (p_out) p_out resistance r p_out v+ = +12v, i p_out = 100ma t a = +25 n c 0.88 1.2 i t a = +125 n c 1.7 v+ = +4.5v, i p_out = 100ma t a = +25 n c 0.91 1.25 t a = +125 n c 1.75 output leakage current i leakp v p_out = 0v 0.01 1 f a peak output current i peakn c l = 22nf 3.0 a logic inputs (in+, in-) logic-high input voltage v ih max15070a 2.0 v MAX15070B 4.25 logic-low input voltage v il max15070a 0.8 v MAX15070B 2.0 logic-input hysteresis v hys max15070a 0.2 v MAX15070B 0.9 logic-input leakage current v in+ = v in- = 0v or v+, max15070a 0.02 f a logic-input bias current v in+ = v in- = 0v or v+, MAX15070B 10 input capacitance 10 pf switching characteristics for v+ = +12v (figure 1) rise time t r c l = 1nf 6 ns c l = 5nf 22 c l = 10nf 36 fall time t f c l = 1nf 4 ns c l = 5nf 11 c l = 10nf 17 turn-on delay time t d-on c l = 1nf (note 4) 7 11 17 ns turn-off delay time t d-off c l = 1nf (note 4) 7 12 18 ns break-before-make time t bbm 2 ns switching characteristics for v+ = +4.5v (max15070a only) (figure 1) rise time t r c l = 1nf 5 ns c l = 5nf 16 c l = 10nf 25 fall time t f c l = 1nf 4 ns c l = 5nf 10 c l = 10nf 14 turn-on delay time t d-on c l = 1nf (note 4) 7 13 21 ns turn-off delay time t d-off c l = 1nf (note 4) 7 14 22 ns break-before-make time t bbm 2 ns thermal characteristics thermal shutdown temperature rising (note 4) 166 n c thermal-shutdown hysteresis (note 4) 13 n c
max15070a/MAX15070B 7a sink, 3a source, 12ns, sot23 mosfet drivers 4 typical operating characteristics (c l = 1000pf, t a = +25 n c, unless otherwise noted. see figure 1.) rise time vs. supply voltage max15070a toc01 supply voltage (v) rise time (ns) 12 10 8 6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.0 41 4 t a = +125c t a = +25c t a = +85c t a = -40c t a = 0c fall time vs. supply voltage max15070a toc02 supply voltage (v) fall time (ns) 12 10 6 8 2.0 2.5 3.0 3.5 4.5 4.0 5.0 5.5 1.5 41 4 t a = +125c t a = +25c t a = +85c t a = -40c t a = 0c propagation delay (low to high) vs. supply voltage max15070a toc03 supply voltage (v) propagation delay (ns) 12 10 8 6 10 12 14 16 18 8 41 4 t a = +125c t a = +25c t a = +85c t a = -40c t a = 0c propagation delay (high to low) vs. supply voltage max15070a toc04 supply voltage (v) propagation delay (ns) 12 10 8 6 10 12 14 16 18 20 8 41 4 t a = +125c t a = +85c t a = -40c t a = 0c t a = +25c supply current vs. supply voltage max15070a toc05 supply voltage (v) supply current (ma) 12 10 8 6 0.5 1.0 1.5 2.0 2.5 3.0 0 41 4 40khz 75khz 100khz 500khz 1mhz duty cycle = 50% c l = 0 supply current vs. load capacitance max15070a toc06 load capacitance (pf) supply current (ma) 1600 1200 400 800 0.5 1.0 1.5 2.0 3.0 2.5 3.5 4.0 0 0 2000 v+ = 12v f = 100khz duty cycle = 50% supply current vs. temperature max15070a toc07 temperature (c) supply current (ma) 110 95 80 65 50 35 20 5 -10 -25 0.6 0.8 1.0 1.2 1.4 0.4 -40 125 v+ = 12v f = 100khz, c l = 0 duty cycle = 50% max15070a input threshold voltage vs. supply voltage max15070a toc08 supply voltage (v) input threshold voltage (v) 12 10 6 8 0.5 1.0 1.5 2.0 3.0 2.5 3.5 4.0 0 41 4 falling rising max15070a supply current vs. input voltage max15070a toc09 input voltage (v) supply current (ma) 5 4 3 2 1 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0.4 01 4 input low to high input high to low
max15070a/MAX15070B 7a sink, 3a source, 12ns, sot23 mosfet drivers 5 typical operating characteristics (continued) (c l = 1000pf, t a = +25 n c, unless otherwise noted. see figure 1.) input voltage vs. output voltage (v+ = +14v, c l = 5000pf) max15070a toc16 v output 5v/div v in+ 5v/div 20ns/div input voltage vs. output voltage (v+ = +14v, c l = 10,000pf) max15070a toc17 v output 5v/div v in+ 5v/div 20ns/div input voltage vs. output voltage (v+ = +4v, c l = 5000pf) max15070a toc10 v output 2v/div v in+ 2v/div 20ns/div input voltage vs. output voltage (v+ = +4v, c l = 10,000pf) max15070a toc11 v output 2v/div v in+ 2v/div 20ns/div input voltage vs. output voltage (v+ = +4v, c l = 5000pf) max15070a toc12 v output 2v/div v in+ 2v/div 20ns/div input voltage vs. output voltage (v+ = +4v, c l = 10,000pf) max15070a toc13 v output 2v/div v in+ 2v/div 20ns/div input voltage vs. output voltage (v+ = +14v, c l = 5000pf) max15070a toc14 v output 5v/div v in+ 5v/div 20ns/div input voltage vs. output voltage (v+ = +14v, c l = 10,000pf) max15070a toc15 v output 5v/div v in+ 5v/div 20ns/div
max15070a/MAX15070B 7a sink, 3a source, 12ns, sot23 mosfet drivers 6 pin description functional diagram pin configuration 6v + 5 p_out 1 in+ sot23 top view gnd 2 in- 3 n_out 4 max15070a MAX15070B + n n_out p_out in- v+ gnd p break- before- make contro l in+ max15070a MAX15070B pin name function 1 in+ noninverting logic input. connect in+ to v+ when not used. 2 gnd ground 3 in- inverting logic input. connect in- to gnd when not used. 4 n_out driver sink output. open-drain n-channel output. sinks current for power mosfet turn-off. 5 p_out driver source output. open-drain p-channel output. sources current for power mosfet turn-on. 6 v+ power-supply input. bypass v+ to gnd with a 1 f f low-esr ceramic capacitor.
max15070a/MAX15070B 7a sink, 3a source, 12ns, sot23 mosfet drivers 7 detailed description logic inputs the max15070a/MAX15070Bs logic inputs are pro - tected against voltage spikes up to +16v, regardless of the v+ voltage. the low 10pf input capacitance of the inputs reduces loading and increases switching speed. these ics have two inputs that give the user greater flexibility in controlling the mosfet. table 1 shows all possible input combinations. the difference between the max15070a and the MAX15070B is the input threshold voltage. the max15070a has ttl logic-level thresholds, while the MAX15070B has hnm (cmos-like) logic-level thresholds (see the electrical characteristics ). connect in+ to v+ or in- to gnd when not used. alternatively, the unused input can be used as an on/off control input (table 1). undervoltage lockout (uvlo) when v+ is below the uvlo threshold, the n-channel is on and the p-channel is off, independent of the state of the inputs. the uvlo is typically 3.45v with 200mv typi - cal hysteresis to avoid chattering. a typical falling delay of 2 f s makes the uvlo immune to narrow negative tran - sients in noisy environments. driver outputs the ics provide two separate outputs. one is an open- drain p-channel, the other an open-drain n-channel. they have distinct current sourcing/sinking capabilities to inde - pendently control the rise and fall times of the mosfet gate. add a resistor in series with p_out/n_out to slow the corresponding rise/fall time of the mosfet gate. figure 1. timing diagram and test circuit table 1. truth table l = logic-low, h = logic-high. in+ v il 90% 10% t d-off p_out and n_out connected together t d-on t f t r in+ in- v+ v+ c l n_out gnd p_out test circuit timing diagram input output v ih max15070a MAX15070B in+ in- p-channel n-channel l l off on l h off on h l on off h h off on
max15070a/MAX15070B 7a sink, 3a source, 12ns, sot23 mosfet drivers 8 applications information supply bypassing, device grounding, and placement ample supply bypassing and device grounding are extremely important because when large external capac - itive loads are driven, the peak current at the v+ pin can approach 3a, while at the gnd pin, the peak current can approach 7a. v cc drops and ground shifts are forms of negative feedback for inverters and, if excessive, can cause multiple switching when the in- input is used and the input slew rate is low. the device driving the input should be referenced to the ics gnd pin, especially when the in- input is used. ground shifts due to insuffi - cient device grounding can disturb other circuits sharing the same ac ground return path. any series inductance in the v+, p_out, n_out, and/or gnd paths can cause oscillations due to the very high di/dt that results when the ics are switched with any capacitive load. a 1 f f or larger value ceramic capacitor is recommended, bypassing v+ to gnd and placed as close as possible to the pins. when driving very large loads (e.g., 10nf) at minimum rise time, 10 f f or more of parallel storage capacitance is recommended. a ground plane is highly recommended to minimize ground return resistance and series inductance. care should be taken to place the ics as close as possible to the external mosfet being driven to further minimize board inductance and ac path resistance. power dissipation power dissipation of the ics consists of three compo - nents, caused by the quiescent current, capacitive charge and discharge of internal nodes, and the output current (either capacitive or resistive load). the sum of these components must be kept below the maximum power-dissipation limit of the package at the operating temperature. the quiescent current is 0.5ma typical. the current required to charge and discharge the internal nodes is frequency dependent (see the typical operating characteristics ). for capacitive loads, the total power dissipation is approximately: p = c load x (v+) 2 x freq where c load is the capacitive load, v+ is the supply voltage, and freq is the switching frequency. layout information the ics mosfet drivers source and sink large currents to create very fast rise and fall edges at the gate of the switching mosfet. the high di/dt can cause unaccept - able ringing if the trace lengths and impedances are not well controlled. the following pcb layout guidelines are recommended when designing with the ics: ? place one or more 1 f f decoupling ceramic capacitor(s) from v+ to gnd as close as possible to the ic. at least one storage capacitor of 10 f f (min) should be located on the pcb with a low resistance path to the v+ pin of the ics. there are two ac cur - rent loops formed between the ic and the gate of the mosfet being driven. the mosfet looks like a large capacitance from gate to source when the gate is being pulled low. the active current loop is from n_out of the ics to the mosfet gate to the mosfet source and to gnd of the ics. when the gate of the mosfet is being pulled high, the active current loop is from p_out of the ics to the mosfet gate to the mosfet source to the gnd terminal of the decoupling capacitor to the v+ terminal of the decoupling capacitor and to the v+ terminal of the ics. while the charging current loop is important, the discharging current loop is critical. it is important to minimize the physical distance and the impedance in these ac current paths. ? in a multilayer pcb, the component surface layer sur - rounding the ics should consist of a gnd plane con - taining the discharging and charging current loops. chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 6 sot23 u6+1 21-0058 90-0175
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 9 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max15070a/MAX15070B 7a sink, 3a source, 12ns, sot23 mosfet drivers revision history revision number revision date description pages changed 0 11/10 initial release 1 11/11 added max15070aavt/v+ to data sheet 1, 2, 3, 8, 9
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